Air Force

Asynchronous clock multiplexer for circuit board testing

Glitch free, multi-clock, asynchronous control circuit


A scientist at the Air Force Research Lab Information Directorate recently invented a device and method that improves the accuracy and speed in the testing of integrated circuits (ICs). The patented technology is available via patent license agreement to companies that would make, use, or sell it commercially.

IEEE’s Joint Test Action Group (JTAG) developed a 5 pin test access port standard which is commonly referred to as JTAG. The standard is used for a variety of IC and board level tests and for verifying designs.

One of the headaches involved with testing is the heretofore necessity of synchronizing the clocks of the test instrument and the integrated circuit under test. Synchronization has allowed input test vectors to be loaded while the clock is stable so that the IC functions under normal operating conditions.

Now, a scientist from the Air Force’s Information Directorate has devised a scheme and device for glitch-free switching between multiple asynchronous clock sources on an IC. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters is synchronized to the destination clock domain and provides the ability to shut all clocks off for a period of time equal to the longest clock period.

By combining the clocks with an OR gate and gating all clocks off before switching from one clock to another, a glitch-free train of clock pulses can be created from individual clock inputs. Since clock glitches can cause erratic behavior in integrated circuits, this invention allows one to switch between different, asynchronous clocks without causing erratic behavior.

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