Digital I/Q reprocessing demodulator (DIRD)

  • US Patent No. 9628314
  • Issued: April 18, 2017
  • Status: Active

A digital I/Q reprocessing demodulator and a process for significantly reducing arctangent computational loads. This is done by ensuring that all calculations are carried out in the linear part of the curve. The architecture of the demodulator is such that the demodulator 100 utilizes two I/Q stages. The first stage is utilized to determine a phase offset with regards to the free-running I/Q clocks. In the second processing stage, the phase of the I/Q reference signals are phase shifted based on the initial estimate such that the incoming carrier signal is nearly in-phase.

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