Army

Distributed heating transistor

Reduced self-heating leading to better performance and longer operation

Electronics

(a) DG-HEMT. Shaded areas (e.g., A–C) are active gate segments while unshaded areas (e.g., D) are inactive segments. In keeping with HEMT dimension designation: vertical scale—width, and horizontal scale—length. The gate length of segments A–C is the same. Inactive areas have a greater length. In comparisons between the DG-HEMT and regular HEMT, the active gate width (sum of segments for the DG-HEMT) is kept the same. (b) Regular HEMT layout (left) and DG-HEMT layout (right).

Electronic devices and integrated circuits have performance limits that are frequently set by the maximum allowable current density, voltage/electric field, and channel (or junction) temperature.

Self-heating of these devices is undesirable as it reduces performance and lifetime. The channel temperature Tc is correlated with the device lifetime through the Arrhenius equation and may be determined through simulations, theoretical models, or experimentally.

Channel temperature directly affects the bandgap, electron mobility, electron saturation speed, pinch-off voltage, breakdown voltage, transconductance, saturation current, output power, and noise performance. Transistor heating is a primary cause of memory effects which degrade linearity of power amplifiers, especially for modulated signals.

Conventional thermal management approaches such as increasing gate-pitch dimension, result in larger device size and performance degradation, especially at millimeter-wave frequencies.

To address heating issues in transistors, Army scientists and engineers have developed a distributed heating transistor with heat-generating regions separated into several active and inactive sections, thereby reducing self-heating. This novel design may be incorporated into field effector transistors (FETs), bipolar junction transistors (BJTs).

Simulations and experimental verification indicate a significant heat reduction as a result of these structures leading to improvements in device performance.

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