Air Force

Enhanced hardware security for fabless ICs

Circuit-level technique that can strongly resist data leakage

Software & Information Technology

Image credit: Starkus01

Due to increasing cost of semiconductor manufacturing, many chip companies have gone fabless and rely on external facilities in foreign countries to produce integrated circuits, a market trend known as fabless IC.

Unfortunately, not all of these facilities can be considered trustworthy and through theft of the chip designs, these fabs may be a conduit for the injection of malicious modifications to the circuitry – hardware trojans (HTs) that compromise the security of the system.

One common objective of HTs is to establish a side channel for data leakage by radio transmission. Through this type of HT, scanned and captured data such as encryptions keys are relayed to the third party. There are an array of defensive measures to counter HTs but these can be skirted if the attackers gain access to the physical chip and can reverse engineer the hardware between fabrication runs.

To further combat HTs, Air Force engineers have developed Randomized Encoding of Combinational Logic for Resistance to Data Leakage (RECORD) – a scheme of temporarily randomized encoding for combinational logic that, with the aid of quilt packaging (low insertion loss, chip-to-chip interconnects), aims to prevent attackers from interpreting the data.

With this approach, generic I/O RECORD modules are pre-fabricated at a secure facility while the chip design is sent off to be fabricated at a third party facility of unknown trustworthiness. This fabricated die is returned from the third party facility and mated with the I/O dies to form a finished chip in a secured facility. To further frustrate attackers the exact placement of I/O modules can be altered chip-to-chip to produce different input patterns, without affecting overall chip function.

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