FETs thermal resistance is essential to their performance in amplifiers, semiconductors, and integrated circuits. Image Credit: Republica on Pixabay
Army Research Laboratory scientist invents a new closed-form model based on device geometry for quickly and accurately simulating FET thermal resistance. The patented technology is available via license agreement to companies that would make, use, or sell it commercially.
The reliability and performance of FETs and monolithic microwave integrated circuits (MMICs) depend critically on the operating channel temperature. Lower power densities for multi-finger devices are mainly due to thermal effects. The device performance is thus critically affected by self-heating. The maximum allowed channel temperature primarily drives the design of the cooling system, device package, and maximum direct current/radio frequency (DC/RF) power limitations. Therefore, an accurate estimate of channel temperature is highly desirable during the design phase of the device or circuit.
One method to describe temperature behavior is using a 3D Laplace equation. However, solving Laplace’s equation using numerical methods requires considerable effort and time does not allow for interactive optimization of the device configuration during MMIC designs and is cost-prohibitive. Instead, many designers use simplified models or formulas to relate the device’s geometrical structure to the thermal resistance. One popular method is an approximation based on Fourier’s conduction law. Unfortunately, a significant drawback of using these simplified models is the inaccuracy of the results.
ARL researcher Ali Mohamed Darwish developed a simple, accurate method of estimating channel temperatures for FETs based on device geometry, configuration, and material parameters. The process gathers geometrical values corresponding to the FET structure and associates them to the elliptical cylinder and prolate spheroidal coordinates to provide a closed-form expression. The closed-form model can be readily used by device and MMIC designers to optimize the geometry and configuration. This method accelerates the design cycle by achieving the desired electrical and thermal performance without invoking complex, time-consuming, and often non-converging numerical techniques.
Benefits
- Results can be incorporated into model-based CAD programs to optimize thermal performance and accelerate the design cycle
- Excellent agreement has been demonstrated between the new model and numerical simulations across multiple variables, such as substrate thickness, gate pitch, width, and length
- Works for FETs comprised of various semiconductor materials (such as GaAs, Si, and SiGe)
The Opportunity
- Businesses can commercialize the technology by licensing U.S. Patent 7,655,944 from the Army
- TechLink guides businesses through evaluation and licensing; services provided at no cost