Air Force

FIFO hardware buffer for microprocessor

Efficient means to handle queued data packets characterized by high data rates

Software & Information Technology

In computer science, FIFO is an acronym for first in, first out – a common method for organizing and manipulating a data buffer as a queue. In a FIFO implementation, processing of data structures that are input to a data buffer is analogous to servicing a queue on a first-come, first-served basis. Communication network bridges, switches, and routers used in computer networks employ FIFO buffers to temporarily store data packets as they await service from limited core processors. In network architectures, multiple FIFO buffers may be dedicated to serving a single network connection and may be designed to simultaneously and independently queue different types of information. As data traffic on networks expands, available processor cycles get scarce resulting in delays within the data pipeline leading to dropped data from the buffer and corrupted data streams.

As a solution to the above, Air Force scientists have developed a microcontroller to convert a simple FIFO mechanism into a powerful tool to map data into memory, transform data representation, or forward data across the computing architecture. This FIFO abstraction and mapping into simple processor instructions allows a low power processor to more efficiently manipulate incoming and outgoing data. In this approach, the management of the queue is off-loaded from the processor core to the FIFO controller. The processor core interacts with the hardware FIFO using existing cache control signals to handle exceptions arising from an empty or full FIFO.

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