The U.S. Navy has developed a novel technology to accelerate the transmission of data. The invention has useful commercial applications and is available to qualified businesses and entrepreneurs for use in new products.
Digital logic devices like graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are becoming more powerful and more capable of generating and processing large amounts of data. One of the challenges associated with this increased capacity is the ability to transfer that large amount of data on and off the logic device.
Processors cannot typically be interrupted to immediately receive large amounts of data. Instead, data is placed into an easily accessed memory buffer, and the processor is notified to pick up the data when available. If using a fixed length payload and both the sending and receiving devices know the size, transfers become simplified because the processor knows how much data it should be retrieved from the buffer. Additionally, if the rate the data is being transferred is known, the processor knows how many transfers need to take place before the buffer overflows. These both represent problems that are not easily overcome for variable-length payloads.
In view of the above, Navy scientists have devised a format agnostic data transfer circuit that can be adapted to efficiently transfer both fixed and variable data sequences between different types of logic devices. This is done in a way that is payload and protocol insensitive, meaning that the circuit does not rely on a format such as contextual information like data length fields embedded within the payload itself.
Many real-time embedded systems can have increasing digital logic capabilities while clock speed is staying relatively stagnant. Because of this, the interface of the new circuit takes advantage of increased logic capabilities, while reducing the loading on the typically over-taxed CPU. This is especially important for real-time applications.
The novel design provides a single generic circuit that is reconfigurable to provide a highly optimized transfer for most payload types and is thus ideal for configurations that need maximum flexibility and performance. Examples of this are Systems on a Chip (SoC), and Systems in Package (SiP) that tightly couple processors with highly capable and reconfigurable logic designs like FPGAs.
There are many hardware acceleration applications of this technology including, but not limited to Software Defined Radio, Software Defined Networking, SoCs and SiPs development, high-speed financial transactions, cloud computing, data center acceleration, and remote sensing applications.
- Does not require data to be formatted in a particular manner
- Can reduce processor resource utilization for both variable and fixed length payloads
- Increases software security and data integrity by implementation of hardware buffer tracking mechanisms
- Cost effective and easy to implement
- Can be used in soft (FPGA) or hard (ASIC) platform logic
- Businesses can productize this invention by licensing US patent 10,127,185 from the Navy
- Potential for collaboration with Navy researchers
- License fees paid to the Navy are negotiated as part of the license application
- TechLink navigates businesses through licensing at no cost