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Most high-speed switch architectures for computing and signal processing networks require large amounts of buffer space or high-speed memory access. If this buffer space is external to the switch IC, such as in the form of SDRAM, gigabits of data can be stored in a single external chip. However the performance will be limited by the access time to the memory, and highly efficient memory access control is required as well. For these reasons, when the memory is external to the switch chip, there is a lower bound on the latency through the switch.
Internal memory is faster than external memory but expensive in terms of chip real estate and limited in size. One of the logic designer’s biggest challenges is effectively utilizing the memory present within an ASIC or FPGA. In addition to being a limited resource, memory blocks internal to the chip are not capable of running at speeds required by the shared medium switches and other fast packet switch architectures, which require a minimum speed of twice the link rate.
Addressing this void in the technology field, Navy scientists have developed a low latency switch architecture for packet switched networks. This switch architecture comprises a combination of input buffers capable of avoiding head-of-line blocking at the input ports for the switch and also allows for a packet to be passed by the switch fabric on to the output port provided there is a free buffer at the output port. The switch architecture also includes an internal switch interconnect capable of allowing different input ports to access a single output simultaneously. The approach improves packet scheduling and routing thus ensuring lower latency across the network and is compliant with a wide variety of protocols.
- Multiple input ports can write simultaneously and independently to a single output port and access input port buffers
- Multiple output ports can simultaneously and independently receive packets from input port buffers and access history (output) buffers
- Prevents head-of-line blocking in packet queues
- Switch architecture is simple enough to be implemented in relatively few gates
- Switch was designed for the RapidIO protocol, but provides improved performance in other switched fabrics as well
- US patent 7,433,363 available for express licensing