Microprocessors installed in our everyday computing devices have not tried to balance hardware performance with operating system (OS) performance. But doing so can lead to optimizations that result in a higher performance OS, and lower power consumption. The cost is a modest increase in hardware complexity.
Army researchers have developed a microprocessor architecture to address the above optimization needs. The OS friendly microprocessor architecture (OSFA) parallelizes the operations typically used in software by an OS to significantly improve the performance of an operating system context switch. A context (or process) switch is the change of the CPU from one process or thread to another. A second benefit of the new architecture is hardware based information assurance for enhanced security. By extending the traditional Unix file permissions bits down to each register, each memory cache bank, and each cache memory bank address, the processor provides hardware level information assurance.
The architecture consists of four digital memory access (DMA)/cache controller banks connected to a microprocessor pipeline. The OSFA is essentially a switched set of cache memory banks in a pipeline configuration. The pipeline DMA/cache banks and controllers provide higher performance and lower power requirements through pipelining and parallelism. Cache bank controllers are configured to only write one block at a time to and from the processor pipeline. This pipeline caching structure also allows for the execution pipeline to run at full speed while hardware controllers provide cache to memory copy operations in parallel.
In summary, the OSFA provides a substantial increase in processor performance at 13% lower power compared to the conventional processor architecture. Researchers estimate that the configuration is approximately four times more efficient than the conventional architecture.
The hardware level security of this architecture may benefit such devices as IT servers, banking computers, network appliances, ATM machines, network storage devices, secure web servers, safety-critical computers, and VPNs. Low-power options offered by this technology could be used in smartphones, tablets, and power limited embedded computers.
This US patent 9,122,610 is related to US application number 20170300719.
- Significantly reduces the cost of an operating system context switch (1 to 10 CPU cycles is possible)
- Provides hardware level information assurance
- Reduces processor power requirements
- The architecture can also be extended to multiprocessor and multi-core configurations
- US patent 9,122,610 available for license
- Potential for collaboration with Army researchers